Optimized design of a 4-bits absolute-value detector based on linear programming

. Nowadays, neural signal acquisition systems are constantly developing, and spike classification algorithms have been widely studied and concerned. This paper designed a practical spike detection circuit, named as the absolute value detector. Project is committed to adopting only simple gate circuits, by using Morgan ’ s theorem to optimize the circuit structure, so that we can ensure that the detector has the following several advantages, simple and beautiful, easy to understand, powerful performance. In addition, this paper also considered the optimization of performance including latency and energy consumption. The increase of Vdd will increase the energy consumption and reduce the delay, while the increase of size will reduce the energy consumption and increase the delay. Using MATLAB software for linear programming, Under the condition of a 1.5-fold increase in the delay, and then adjusting Vdd and size, energy consumption was down by 78 percent.


Introduction
With the development of electronic technology, all electronic products are rapidly updated while the demand grows rapidly, increasing the circuit speed and reducing the circuit energy consumption has become a hot topic of research [1].Nowadays, due to the limitations of Moore's law, researchers used to rely on reducing the size of the chip to obtain smaller energy, and the use of the delayed method is no longer effective.Therefore, the use of better circuit design to achieve this goal has become the main research direction of today's researchers [2].The 4-bit absolute value detector is the main basic unit of the neural signal acquisition system, it is also widely applied in the chip's ALU unit, so the optimization of the 4-bit absolute value detector is of great practical value, which will greatly improve the chip's operational efficiency.Although this is only a small part of the chip, the hard work of researchers can create a higher speed computing chip [3].This paper focuses on the optimization of the circuit topology, the calculation of delay and energy, and the optimization of performance.
In the next session, it will present the design and optimization of the circuit topology, calculation of delays, sizing, and power supply (Vdd) optimization.Specifically, the second part is about the design of the circuit topology, which consists of a magnitude calculator and a comparator.The third part is about the calculation of delay.First, the circuit topology of the second part is utilized to determine its critical path delay, and then the logic effort formula is used to calculate its circuit delay and the detailed size of each logic gate.The last part is about energy optimization.In total, there are three different approaches, size only optimization, voltage only optimization and size plus voltage simultaneous optimization to achieve reduced energy consumption.

General idea
This project ultimately needs to design a 4-bit "absolute value detector" with a minimum delay energy 50% (1.5 times) longer than the minimum delay [4].Because we can have a better energy performance while the delay is not significantly increased as a static logic circuit [5][6].This is an important characteristic to consider for its use in reversible neural signal processing arithmetic and logic units (ALUs) [7].Where "delay" refers to the propagation delay on the critical path, because the delay of other paths is less important, and "energy" refers to the total energy obtained from the VDD under a given input probability distribution [8].In this paper, gate size and supply voltage scaling are used as variables to optimize the energy consumption.The final designed circuit is divided into two main parts, the first part derives the magnitude value of the 4-bit random variable input and the second part compares the magnitude value with the threshold value and outputs a high level if the threshold value is exceeded, otherwise a low level is output.The basic framework diagram is shown in figure 1 [9].

Schematic of magnitude calculator circuit and the design process
First, I list the binary original code corresponding to 4-bits randomly input binary complement in the truth table, and then simplify the simplest expression with Karnaugh map.The truth table and the simplest expression are as follows in table 1.
In order to improve the performance of the circuit, first, the goal of my design is to use fewer gate circuits and share more common parts that can be used together.My method is to change the expression by using Morgan's theorem to get the desired expression; Second, it been known that AND, OR and XOR are not easy to be generate, so this paper transforms them into NAND, NOR which are easy to get [10].Therefore, it get the final expression as follows: According to the expression, the magnitude calculator circuit is shown in Figure .2.This magnitude calculator includes several NOR, NAND, XOR and inverter.

Schematic of 3-bits comparator circuit and the design process
In this module, I have designed a three-bit comparator which needs to compare the amplitude calculated(A2A1A0) in the previous stage with the threshold(B2B1B0) value and outputs a high level if it is greater than the threshold value, otherwise it outputs a low level.I used the same method by first listing the output expression and building it out in a circuit diagram with the following expression.Finally, we can get the following comparator circuit diagram Figure .3.This is a 3-bit comparator circuit with a critical path number of 5 stages from A2 to Out.

Total circuit schematic
We connect all the circuit topology above to get the final 4-bits absolute value Detector.The total circuit schematic as shown in figure 4 below.This total circuit is in the operating state with the input of 0001.

Detect the critical path
The critical path is a complete conduction circuit with the most stages.We can find that the critical path is as shown in the figure 5   Figure 5 shows the overall schematic design of the 4-bits absolute value comparator with the critical path indicated in yellow.The total number of stages in the critical path is 13 stages.We will calculate the critical path delay in the next section.

Delay calculation
According to Figure 5 in the previous section, there are a total of 13 phases for the critical path from the input port to the output port.We assume that the capacitance of an inverter as a unit of the cin, and we assume that the output load is a 32 Cin load.Critical path circuit, as shown in Figure 6.Before the input port there is a non-gate as an input load with a capacitance of Cin and after the output port there is a capacitive load of 32 times Cin.On this basis, the circuit designed in this project uses a critical path containing 13 stages with an output load that is 32 times the input load.Also to be taken into account during the delay calculation is the fact that there are 2 branches in this critical path.In this paper, it is assumed that Wp is equal to 650 nm and WN is equal to 430 nm for unit size inverter.then this paper can get WP: WN is equal to 1.5.drawing the specific gate circuit diagrams and analyzing them, it is not difficult to get their parasitic and logical efforts.The gate circuit is analyzed as shown in follow figures 7. For the critical path, this paper calculates the overall logical effort of this path in the following way (the unit i in the following equations, represents the ith level gate circuit): The first part is the logical effort generated on the path.The specific calculation formula is as follows: The degree of total ladder was calculated using the ratio of the terminal load capacitor size to the front load capacitor size: The second part is the logical effort generated on the branch.The specific calculation formula is as follows: Ultimately, the logical effort of the entire critical path is as follows: 11232.59 GHB F = = (10) The total number of stages N is as follows: When the logical effort at the same value at each stage, the delay can get minimum value, the logical effort of stage is obtained by dividing the total logical effort by N times: Using following formula, the lowest delay for the entire critical path is obtained as follows: In addition, we need to calculate the data in the table below, the size, delay, and energy consumption of each stage, for the subsequent optimization work.
The specific calculation formula is as follows (the default Vdd value is equal to 1):

energy calculation
The energy consumption of the whole critical circuit is the accumulation of the energy consumption of each circuit stage including the energy consumption of the end loads, and it is not difficult for us to calculate the total energy consumption.

performance optimization
Based on our calculations above, we got the minimum delay for the circuit design, but we have not optimized the energy yet, we decided to sacrifice our delay to reduce the total energy consumption, the maximum delay we can get is 1.5 times our current minimum delay and we assumed that the maximum supply voltage is 1.

Only Vdd optimization
Using expression shown below, we can obtain the voltage value after only optimized Vdd: Initial condition: Computational process: With a delay time of 1.5 times its minimum, only optimizing Vdd reduces the energy consumption to 88.72, a reduction of about 39.8%.

Size optimization
This part of the optimization is to adjust the size in order to reduce the energy use, and the optimized data for the specific dimensions are shown in Table 3 (L will be calculated later).The method used is to first set the size of all stages before the last stage to 1, and invert the size of the last stage by calculating the delay as follows: With a delay time of 1.5 times its minimum value, only optimizing the size reduces the energy consumption to 68.14, a reduction of about 46%.

Vdd and size optimization together
At this part, we need to optimize both Vdd and size, but the increase of Vdd will increase the energy consumption and reduce the delay, while the increase of size will reduce the energy consumption and increase the delay.So we use the linear programming to find the optimal solution.The conditional formulas for the linear programming are as follows: Objective function: By optimizing both Vdd and size by linear programming using MATLAB software, we can finally get a reduction in energy consumption to 31.94, a reduction of about 78%.

Summary of the optimization section
It is not difficult to find that the best effect is to optimize both Vdd and size at the same time.We will show the results of the above three parts together in Table 4.It can be seen from the above table that it sacrifices 50% of the minimum delay, and simultaneously optimize Vdd and size, which can effectively reduce the energy consumption by 78%.This is very worthwhile.

Conclusion
The absolute value detector designed in this paper is divided into absolute value acquisition module and comparator module.In this project, only simple NOR gates, NAND gates, and XOR gates are used to implement the circuit function and optimization of expression and circuit structure is done.In addition, the optimization of performance (delay and energy consumption) is also considered in this paper.In this paper, When calculating the delay of its entire circuit, we only consider the delay of its critical path and ignore the delay of other paths, because the delay of other paths is less important.After rigorous calculations, we found that using MATLAB software for linear programming, the energy consumption decreased by 78% with a 1.5 times increase in delay while adjusting Vdd and size.With the above calculations we can also summarize the following features that allow us to create a static logic circuit that consumes less energy without a significant increase in delay, a feature that can be fully used in reversible neural signal processing algorithms and logic units.Overall, the absolute value detector designed in this project performs well and is optimized beyond expectations.

Figure 5 .
Figure 5. Critical path with yellow marked.

Table 2 .
Detail datas of each stage.

Table 3 .
Size Optimization data.